c9320eb9db
radio_tx_burst(): captures current slot, calls fhss_next_channel() to advance the sequence, sets channel, transmits ptt_frame_t, then holds the dwell window via TIMER0 so the receiver has the full 2 ms to listen. radio_rx_burst(): advances to the same channel, enables RX, waits for EVENTS_END or TIMER0 COMPARE0 expiry. On a valid CRC the ptt_frame_t is returned; caller syncs FHSS with fhss_set_slot(frame.slot + 1). TIMER0: configured once in radio_init() (MODE=Timer, BITMODE=16-bit, PRESCALER=4 -> 1 MHz tick, CC[0]=2000 -> 2 ms, COMPARE0_STOP shortcut). fhss.c: replace zero key with a non-trivial 128-bit value; add fhss_set_slot() and fhss_get_slot() for RX synchronisation. power.c: add BUTTON_ACTIVE_LOW flag (default 1 = pull-up + GND button); configure PIN_CNF accordingly; implement power_button_pressed() via NRF_P0->IN. regs.h: add gpio_pin_cnf_t with GPIO_PULL_* constants. main.c: tight PTT loop -- radio_tx_burst() while button held, otherwise radio_rx_burst() with slot sync on reception. No WFI in RX mode.
177 lines
6.5 KiB
C
177 lines
6.5 KiB
C
/**
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* @file regs.h
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* @brief Hardware register bitfield unions for nRF52840 peripherals.
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*
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* Layout is guaranteed correct only with arm-none-eabi-gcc (LSB-first
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* bitfields). Bit ranges match nRF52840 Product Specification v1.7.
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*/
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#pragma once
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#include <stdint.h>
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/* GPIOTE */
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/** @brief GPIOTE CONFIG[n]: channel configuration register. */
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typedef union {
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struct {
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uint32_t MODE : 2; /* [1:0] 0=Disabled 1=Event 3=Task */
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uint32_t : 6; /* [7:2] reserved */
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uint32_t PSEL : 5; /* [12:8] pin number within port */
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uint32_t PORT : 1; /* [13] 0=Port0 1=Port1 */
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uint32_t : 2; /* [15:14] reserved */
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uint32_t POLARITY : 2; /* [17:16] 0=None 1=LoToHi 2=HiToLo 3=Toggle */
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uint32_t : 2; /* [19:18] reserved */
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uint32_t OUTINIT : 1; /* [20] initial output value for Task mode */
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uint32_t : 11; /* [31:21] reserved */
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} bit;
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uint32_t reg;
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} gpiote_config_t;
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#define GPIOTE_MODE_DISABLED 0u
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#define GPIOTE_MODE_EVENT 1u
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#define GPIOTE_MODE_TASK 3u
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#define GPIOTE_POL_NONE 0u
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#define GPIOTE_POL_LOTOHI 1u
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#define GPIOTE_POL_HITOLO 2u
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#define GPIOTE_POL_TOGGLE 3u
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/** @brief GPIOTE INTENSET / INTENCLR: interrupt enable register. */
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typedef union {
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struct {
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uint32_t IN0 : 1; /* [0] channel 0 input event */
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uint32_t IN1 : 1; /* [1] channel 1 input event */
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uint32_t IN2 : 1; /* [2] */
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uint32_t IN3 : 1; /* [3] */
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uint32_t IN4 : 1; /* [4] */
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uint32_t IN5 : 1; /* [5] */
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uint32_t IN6 : 1; /* [6] */
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uint32_t IN7 : 1; /* [7] */
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uint32_t : 23; /* [30:8] reserved */
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uint32_t PORT : 1; /* [31] PORT event */
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} bit;
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uint32_t reg;
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} gpiote_inten_t;
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/* RADIO */
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/** @brief RADIO FREQUENCY: RF channel selection register. */
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typedef union {
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struct {
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uint32_t FREQUENCY : 7; /* [6:0] offset from base frequency in MHz */
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uint32_t : 1; /* [7] reserved */
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uint32_t MAP : 1; /* [8] 0: base=2400 MHz 1: base=2360 MHz */
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uint32_t : 23; /* [31:9] reserved */
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} bit;
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uint32_t reg;
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} radio_frequency_t;
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#define RADIO_MAP_DEFAULT 0u /* channel n -> 2400+n MHz */
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#define RADIO_MAP_BLE 1u /* channel n -> 2360+n MHz */
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/** @brief RADIO TXPOWER: transmit power register. */
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typedef union {
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struct {
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int32_t TXPOWER : 8; /* [7:0] signed dBm: +8, +7, +6, +5, +4, +3, +2,
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0, -4, -8, -12, -16, -20, -40 */
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uint32_t : 24; /* [31:8] reserved */
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} bit;
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uint32_t reg;
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} radio_txpower_t;
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/** @brief RADIO MODE: data rate and modulation register. */
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typedef union {
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struct {
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uint32_t MODE : 4; /* [3:0] 0=NRF_1Mbit 1=NRF_2Mbit 4=BLE_1Mbit ... */
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uint32_t : 28; /* [31:4] reserved */
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} bit;
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uint32_t reg;
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} radio_mode_t;
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#define RADIO_MODE_NRF_1MBIT 0u
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#define RADIO_MODE_NRF_2MBIT 1u
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#define RADIO_MODE_BLE_1MBIT 4u
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/** @brief RADIO PCNF0: packet configuration register 0 (header fields). */
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typedef union {
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struct {
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uint32_t LFLEN : 4; /* [3:0] length of LENGTH field in bits */
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uint32_t : 4; /* [7:4] reserved */
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uint32_t S0LEN : 1; /* [8] length of S0 field in bytes (0 or 1) */
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uint32_t : 7; /* [15:9] reserved */
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uint32_t S1LEN : 4; /* [19:16] length of S1 field in bits */
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uint32_t S1INCL : 1; /* [20] include S1 field in RAM even if zero length */
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uint32_t : 3; /* [23:21] reserved */
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uint32_t PLEN : 1; /* [24] 0=8-bit preamble 1=16-bit preamble */
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uint32_t : 6; /* [30:25] reserved */
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uint32_t CRCINC : 1; /* [31] include CRC in LENGTH field */
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} bit;
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uint32_t reg;
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} radio_pcnf0_t;
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/** @brief RADIO PCNF1: packet configuration register 1 (payload and address). */
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typedef union {
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struct {
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uint32_t MAXLEN : 8; /* [7:0] maximum payload length in bytes */
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uint32_t STATLEN : 8; /* [15:8] static length added to payload */
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uint32_t BALEN : 3; /* [18:16] base address length (2-4 bytes) */
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uint32_t : 5; /* [23:19] reserved */
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uint32_t ENDIAN : 1; /* [24] 0=little-endian 1=big-endian */
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uint32_t WHITEEN : 1; /* [25] 1=enable data whitening */
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uint32_t : 6; /* [31:26] reserved */
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} bit;
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uint32_t reg;
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} radio_pcnf1_t;
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/** @brief RADIO CRCCNF: CRC configuration register. */
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typedef union {
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struct {
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uint32_t LEN : 2; /* [1:0] 0=disabled 1=1 byte 2=2 bytes 3=3 bytes */
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uint32_t : 6; /* [7:2] reserved */
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uint32_t SKIPADDR : 1; /* [8] 1=skip address field in CRC calculation */
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uint32_t : 23; /* [31:9] reserved */
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} bit;
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uint32_t reg;
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} radio_crccnf_t;
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#define RADIO_CRCCNF_LEN_DISABLED 0u
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#define RADIO_CRCCNF_LEN_ONE 1u
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#define RADIO_CRCCNF_LEN_TWO 2u
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#define RADIO_CRCCNF_LEN_THREE 3u
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/** @brief RADIO SHORTS: hardware shortcut register. */
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typedef union {
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struct {
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uint32_t READY_START : 1; /* [0] READY -> TASKS_START */
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uint32_t END_DISABLE : 1; /* [1] END -> TASKS_DISABLE */
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uint32_t DISABLED_TXEN : 1; /* [2] DISABLED -> TASKS_TXEN */
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uint32_t DISABLED_RXEN : 1; /* [3] DISABLED -> TASKS_RXEN */
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uint32_t ADDRESS_RSSISTART : 1; /* [4] ADDRESS -> TASKS_RSSISTART */
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uint32_t END_START : 1; /* [5] END -> TASKS_START */
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uint32_t ADDRESS_BCSTART : 1; /* [6] ADDRESS -> TASKS_BCSTART */
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uint32_t : 1; /* [7] reserved */
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uint32_t DISABLED_RSSISTOP : 1; /* [8] DISABLED -> TASKS_RSSISTOP */
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uint32_t : 23; /* [31:9] reserved */
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} bit;
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uint32_t reg;
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} radio_shorts_t;
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/* GPIO */
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/** @brief GPIO PIN_CNF[n]: pin configuration register. */
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typedef union {
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struct {
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uint32_t DIR : 1; /* [0] 0=Input 1=Output */
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uint32_t INPUT : 1; /* [1] 0=Connect 1=Disconnect */
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uint32_t PULL : 2; /* [3:2] 0=Disabled 1=Pulldown 3=Pullup */
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uint32_t : 4; /* [7:4] reserved */
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uint32_t DRIVE : 3; /* [10:8] 0=S0S1 standard drive */
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uint32_t : 5; /* [15:11] reserved */
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uint32_t SENSE : 2; /* [17:16] 0=Disabled 2=SenseHigh 3=SenseLow */
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uint32_t : 14; /* [31:18] reserved */
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} bit;
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uint32_t reg;
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} gpio_pin_cnf_t;
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#define GPIO_PULL_DISABLED 0u
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#define GPIO_PULL_PULLDOWN 1u
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#define GPIO_PULL_PULLUP 3u
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