ptt-fhss
Bare-metal PTT firmware for nRF52840 with FHSS
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regs.h
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1
8#pragma once
9#include <stdint.h>
10
11/* GPIOTE */
12
14typedef union {
15 struct {
16 uint32_t MODE : 2; /* [1:0] 0=Disabled 1=Event 3=Task */
17 uint32_t : 6; /* [7:2] reserved */
18 uint32_t PSEL : 5; /* [12:8] pin number within port */
19 uint32_t PORT : 1; /* [13] 0=Port0 1=Port1 */
20 uint32_t : 2; /* [15:14] reserved */
21 uint32_t POLARITY : 2; /* [17:16] 0=None 1=LoToHi 2=HiToLo 3=Toggle */
22 uint32_t : 2; /* [19:18] reserved */
23 uint32_t OUTINIT : 1; /* [20] initial output value for Task mode */
24 uint32_t : 11; /* [31:21] reserved */
25 } bit;
26 uint32_t reg;
28
29#define GPIOTE_MODE_DISABLED 0u
30#define GPIOTE_MODE_EVENT 1u
31#define GPIOTE_MODE_TASK 3u
32#define GPIOTE_POL_NONE 0u
33#define GPIOTE_POL_LOTOHI 1u
34#define GPIOTE_POL_HITOLO 2u
35#define GPIOTE_POL_TOGGLE 3u
36
38typedef union {
39 struct {
40 uint32_t IN0 : 1; /* [0] channel 0 input event */
41 uint32_t IN1 : 1; /* [1] channel 1 input event */
42 uint32_t IN2 : 1; /* [2] */
43 uint32_t IN3 : 1; /* [3] */
44 uint32_t IN4 : 1; /* [4] */
45 uint32_t IN5 : 1; /* [5] */
46 uint32_t IN6 : 1; /* [6] */
47 uint32_t IN7 : 1; /* [7] */
48 uint32_t : 23; /* [30:8] reserved */
49 uint32_t PORT : 1; /* [31] PORT event */
50 } bit;
51 uint32_t reg;
53
54/* RADIO */
55
57typedef union {
58 struct {
59 uint32_t FREQUENCY : 7; /* [6:0] offset from base frequency in MHz */
60 uint32_t : 1; /* [7] reserved */
61 uint32_t MAP : 1; /* [8] 0: base=2400 MHz 1: base=2360 MHz */
62 uint32_t : 23; /* [31:9] reserved */
63 } bit;
64 uint32_t reg;
66
67#define RADIO_MAP_DEFAULT 0u /* channel n -> 2400+n MHz */
68#define RADIO_MAP_BLE 1u /* channel n -> 2360+n MHz */
69
71typedef union {
72 struct {
73 int32_t TXPOWER : 8; /* [7:0] signed dBm: +8, +7, +6, +5, +4, +3, +2,
74 0, -4, -8, -12, -16, -20, -40 */
75 uint32_t : 24; /* [31:8] reserved */
76 } bit;
77 uint32_t reg;
79
81typedef union {
82 struct {
83 uint32_t MODE : 4; /* [3:0] 0=NRF_1Mbit 1=NRF_2Mbit 4=BLE_1Mbit ... */
84 uint32_t : 28; /* [31:4] reserved */
85 } bit;
86 uint32_t reg;
88
89#define RADIO_MODE_NRF_1MBIT 0u
90#define RADIO_MODE_NRF_2MBIT 1u
91#define RADIO_MODE_BLE_1MBIT 4u
92
94typedef union {
95 struct {
96 uint32_t LFLEN : 4; /* [3:0] length of LENGTH field in bits */
97 uint32_t : 4; /* [7:4] reserved */
98 uint32_t S0LEN : 1; /* [8] length of S0 field in bytes (0 or 1) */
99 uint32_t : 7; /* [15:9] reserved */
100 uint32_t S1LEN : 4; /* [19:16] length of S1 field in bits */
101 uint32_t S1INCL : 1; /* [20] include S1 field in RAM even if zero length */
102 uint32_t : 3; /* [23:21] reserved */
103 uint32_t PLEN : 1; /* [24] 0=8-bit preamble 1=16-bit preamble */
104 uint32_t : 6; /* [30:25] reserved */
105 uint32_t CRCINC : 1; /* [31] include CRC in LENGTH field */
106 } bit;
107 uint32_t reg;
109
111typedef union {
112 struct {
113 uint32_t MAXLEN : 8; /* [7:0] maximum payload length in bytes */
114 uint32_t STATLEN : 8; /* [15:8] static length added to payload */
115 uint32_t BALEN : 3; /* [18:16] base address length (2-4 bytes) */
116 uint32_t : 5; /* [23:19] reserved */
117 uint32_t ENDIAN : 1; /* [24] 0=little-endian 1=big-endian */
118 uint32_t WHITEEN : 1; /* [25] 1=enable data whitening */
119 uint32_t : 6; /* [31:26] reserved */
120 } bit;
121 uint32_t reg;
123
125typedef union {
126 struct {
127 uint32_t LEN : 2; /* [1:0] 0=disabled 1=1 byte 2=2 bytes 3=3 bytes */
128 uint32_t : 6; /* [7:2] reserved */
129 uint32_t SKIPADDR : 1; /* [8] 1=skip address field in CRC calculation */
130 uint32_t : 23; /* [31:9] reserved */
131 } bit;
132 uint32_t reg;
134
135#define RADIO_CRCCNF_LEN_DISABLED 0u
136#define RADIO_CRCCNF_LEN_ONE 1u
137#define RADIO_CRCCNF_LEN_TWO 2u
138#define RADIO_CRCCNF_LEN_THREE 3u
139
141typedef union {
142 struct {
143 uint32_t READY_START : 1; /* [0] READY -> TASKS_START */
144 uint32_t END_DISABLE : 1; /* [1] END -> TASKS_DISABLE */
145 uint32_t DISABLED_TXEN : 1; /* [2] DISABLED -> TASKS_TXEN */
146 uint32_t DISABLED_RXEN : 1; /* [3] DISABLED -> TASKS_RXEN */
147 uint32_t ADDRESS_RSSISTART : 1; /* [4] ADDRESS -> TASKS_RSSISTART */
148 uint32_t END_START : 1; /* [5] END -> TASKS_START */
149 uint32_t ADDRESS_BCSTART : 1; /* [6] ADDRESS -> TASKS_BCSTART */
150 uint32_t : 1; /* [7] reserved */
151 uint32_t DISABLED_RSSISTOP : 1; /* [8] DISABLED -> TASKS_RSSISTOP */
152 uint32_t : 23; /* [31:9] reserved */
153 } bit;
154 uint32_t reg;
156
157/* GPIO */
158
160typedef union {
161 struct {
162 uint32_t DIR : 1; /* [0] 0=Input 1=Output */
163 uint32_t INPUT : 1; /* [1] 0=Connect 1=Disconnect */
164 uint32_t PULL : 2; /* [3:2] 0=Disabled 1=Pulldown 3=Pullup */
165 uint32_t : 4; /* [7:4] reserved */
166 uint32_t DRIVE : 3; /* [10:8] 0=S0S1 standard drive */
167 uint32_t : 5; /* [15:11] reserved */
168 uint32_t SENSE : 2; /* [17:16] 0=Disabled 2=SenseHigh 3=SenseLow */
169 uint32_t : 14; /* [31:18] reserved */
170 } bit;
171 uint32_t reg;
173
174#define GPIO_PULL_DISABLED 0u
175#define GPIO_PULL_PULLDOWN 1u
176#define GPIO_PULL_PULLUP 3u
GPIO PIN_CNF[n]: pin configuration register.
Definition regs.h:160
uint32_t reg
Definition regs.h:171
uint32_t SENSE
Definition regs.h:168
uint32_t PULL
Definition regs.h:164
uint32_t DRIVE
Definition regs.h:166
uint32_t INPUT
Definition regs.h:163
uint32_t DIR
Definition regs.h:162
GPIOTE CONFIG[n]: channel configuration register.
Definition regs.h:14
uint32_t POLARITY
Definition regs.h:21
uint32_t reg
Definition regs.h:26
uint32_t PSEL
Definition regs.h:18
uint32_t OUTINIT
Definition regs.h:23
uint32_t MODE
Definition regs.h:16
uint32_t PORT
Definition regs.h:19
GPIOTE INTENSET / INTENCLR: interrupt enable register.
Definition regs.h:38
uint32_t reg
Definition regs.h:51
uint32_t IN2
Definition regs.h:42
uint32_t IN6
Definition regs.h:46
uint32_t IN3
Definition regs.h:43
uint32_t IN1
Definition regs.h:41
uint32_t IN5
Definition regs.h:45
uint32_t IN4
Definition regs.h:44
uint32_t PORT
Definition regs.h:49
uint32_t IN0
Definition regs.h:40
uint32_t IN7
Definition regs.h:47
RADIO CRCCNF: CRC configuration register.
Definition regs.h:125
uint32_t LEN
Definition regs.h:127
uint32_t reg
Definition regs.h:132
uint32_t SKIPADDR
Definition regs.h:129
RADIO FREQUENCY: RF channel selection register.
Definition regs.h:57
uint32_t FREQUENCY
Definition regs.h:59
uint32_t reg
Definition regs.h:64
uint32_t MAP
Definition regs.h:61
RADIO MODE: data rate and modulation register.
Definition regs.h:81
uint32_t reg
Definition regs.h:86
uint32_t MODE
Definition regs.h:83
RADIO PCNF0: packet configuration register 0 (header fields).
Definition regs.h:94
uint32_t S1LEN
Definition regs.h:100
uint32_t S0LEN
Definition regs.h:98
uint32_t reg
Definition regs.h:107
uint32_t CRCINC
Definition regs.h:105
uint32_t LFLEN
Definition regs.h:96
uint32_t PLEN
Definition regs.h:103
uint32_t S1INCL
Definition regs.h:101
RADIO PCNF1: packet configuration register 1 (payload and address).
Definition regs.h:111
uint32_t BALEN
Definition regs.h:115
uint32_t WHITEEN
Definition regs.h:118
uint32_t reg
Definition regs.h:121
uint32_t ENDIAN
Definition regs.h:117
uint32_t MAXLEN
Definition regs.h:113
uint32_t STATLEN
Definition regs.h:114
RADIO SHORTS: hardware shortcut register.
Definition regs.h:141
uint32_t ADDRESS_RSSISTART
Definition regs.h:147
uint32_t DISABLED_RXEN
Definition regs.h:146
uint32_t END_DISABLE
Definition regs.h:144
uint32_t READY_START
Definition regs.h:143
uint32_t reg
Definition regs.h:154
uint32_t DISABLED_TXEN
Definition regs.h:145
uint32_t END_START
Definition regs.h:148
uint32_t DISABLED_RSSISTOP
Definition regs.h:151
uint32_t ADDRESS_BCSTART
Definition regs.h:149
RADIO TXPOWER: transmit power register.
Definition regs.h:71
int32_t TXPOWER
Definition regs.h:73
uint32_t reg
Definition regs.h:77